AGENDA

8.30	Arrival: Refreshments and Networking
9.15	Introduction: Mike Bartley, TVS
9.20	Mentor Graphics – Harry Foster, Chief Scientist
10.00	Panel Session: Challenge Papers – Our Top Verification Challenges Infineon Technologies – Tim Blackmore, Senior Staff Engineer in Verification nVidia – Andy Bond, Silicon Functional Verification Manager Broadcom -Geoff Barrett, Technical Director Wolfson Microelectronics – Andre Winkelmann, Principal Design Engineer Dialog Semiconductor – Steve Holloway, Senior Verification Engineer
10.40	Synopsys – Janick Bergeron, Scientist and Fellow
11.00	Refreshments and Networking
11.30	User Presentations Dialog Semiconductor – Steve Holloway, Senior Verification Engineer Imagination Technologies – Theo Drane, Principle Design Engineer Test and Verification Solutions – Francois Cerisier, Manager TVS France
12.30	EVE – Luc Burgun, CEO and President, Emulation & Verification Engineering S.A
13.00	Lunch and Networking
14.00	Jasper Design Automation – Stefan Staber, Staff Field Application Engineer
14.20	Doulos – John Aynsley, CTO
14.40	Cadence – Nick Heaton, Senior System and SoC Solutions Architect
15.10	SpringSoft Inc – Jean-Marc Forey, Technical Marketing Manager
15.40	Refreshments and Networking
16.10	Aldec Inc – Jacek Majkowski, Senior Hardware Engineer
16.40	Panel Session: The EDA response
17.25	Concluding Remarks from Platinum Sponsors (Mentor Graphics, SpringSoft Inc, Cadence, EVE, Aldec)
17.40	Meet the sponsors in the Exhibition Area
18.15	End of Conference