Steve Holloway, Dialog Semiconductors

Name: Steve Holloway

Designation: Senior Verification Engineer at Dialog Semiconductor

Title:  UVM Register Modelling: User Experiences and some Recipes

Abstract: ASIC designs commonly have a large number of on-chip registers which must be verified before tape-out. The UVM methodology includes a register modelling package which is designed to help simplify this task. In order to perform register modelling in UVM, several steps must be followed. These include creating a register model with an automatic generator, capturing “quirky” register behaviour, integrating the register model into a verification environment and writing register test sequences. The UVM register layer is flexible and can be integrated in a number of different ways. This presentation covers our experiences with the UVM register modelling package together with some recipes for creating your own quirky registers.

Biography: Steve Holloway is currently Senior Verification Engineer within the Methodologies group of Dialog Semiconductor.  He has led the verification of various large-scale consumer SoC projects and is experienced with various Hardware Verification Methodologies including eRM, OVM and UVM.  Steve has previously worked for Doulos, NXP and Trident Microsystems.

Verification Futures Conference Presentation                 Video Presentation

Book you place for 2012: