Next week European Semiconductor Engineers will present their major verification challenges. Infineon, Dialog, ST, ST-E, Nvidia, Wolfson, ARM, Lantiq, Freescale, Broadcom and TI will present a total of 36 verification challenges. The challenge for the EDA industry is to respond … Read More
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Verification Futures Conference Series (UK, France and Germany)
The Verification Futures conference series will take place across Europe next month and places are filling up fast!! They follow on from the huge success of last year’s first ever UK Hardware Verification Conference which involved 300 participants from over … Read More
Inward Investment UKTI meetings in Bristol
I am posting with my West of England LEP hat (see http://www.westofenglandlep.co.uk/). I chair the Microelectronics Sector Group and our remit is to encourage sector growth within the region. With that in mind I am working with the UKTI who … Read More
Meet the Cortex-A15 Verification team in Bangalore on May 23rd 2012
TVS is pleased to work with ARM to bring “The Cortex-A15 Verification Story” toBangalore. Bill Greene (Austin CPU Validation Manager, ARM) and Micah McDaniel (Principal Design Engineer, ARM, was the verification lead for the Cortex-A15 processor) have presented at DVClub … Read More
Lies, Damned Lies and Hardware Verification
This relates to a paper I delivered at SNUG in Munch in 2008. It looks at a number of myths that surrounded verification at the time but that still seem relevant today! Verification takes 70% of the design cycle Half … Read More
TVS SDCARD 2.0 OVM VIP showcased in EDA Cafe
TVS SDCARD 2.0 OVM VIP showcased in EDA Cafe
Multicore Challenge 2011
In September 2011 TVS organised the second “Multicore Challenge” in Bristol. The “Multicore Challenge” series of events focus on the challenges the industry faces as it moves to multicore architectures to improve performance without increasing power. Click here for downloads … Read More
DVClub April 2010: Verification of re-used Design IP
The DVClub held on 26th April 2010 in Bristol, Cambridge and Eindhoven, with remote access too, considered “Design IP – help or hindrance to verification?”. “Metrics and methods to determine if your IP has been pre-verified”, Moshik Rubin, Cadence “Integration Verification: Re-Create … Read More
DVClub Oct 2008: Deploying Functional Qualification
Click here to see the slides DVClub 20th Oct 2008