Verification Engineer or Sr. Verification Engineer – ASIC/SOC

Location and Start Date

• Bangalore India –  [Start Date 15^th Aug 2012] – 4 Positions

Education

• B.E in Computer or Electronics Engineering
• M.Tech or PhD an advantage

Skillset

Must Have

• Block and Top level verification know-how
• Verification Plan Development
• System Verilog/OVM or UVM
• Testbench Development
• VHDL/Verilog simulation and debug
• Scripting

Nice to have

• HVL: Specman is a plus
• End to End RTL Functional Verification Concepts
• Understanding of power aware architecture

Experience

Must have

• 2 – 6 Years Of Experience
• Performing feature extraction from a specification
• Coverage closure
• Experience of other HVLs (e.g. System Verilog) and methodologies (e.g. UVM)

Nice to have

• Experience in Mobility, NFC or Multimedia Applications

Job Description

Responsibilities

• Develop Verification Plan and Verification Architecture
• Develop Tests and Testbench
• Implement Functional Coverage Points
• Achieve 100% Functional Coverage
• Develop Verification Plan Documentation and Capture Results of Execution

How To Apply

• Send your CV to hr@testandverification.com

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